DETECTION ALGORITHMS AND ARCHITECTURES FOR WIRELESS SPATIAL MULTIPLEXING INMIMO-OFDM SYSTEMS, ACTA UNIVERSITATIS OULUENSIS C Technica 380
|Kustantaja:||Oulun yliopisto|| |
|Oppiaine:||Tekniikka, matematiikka || |
|Sijainti:||Print Tietotalo|| |
|Tekijät:||MYLLYLÄ MARKUS|| |
The development of wireless telecommunication systems has been rapid during the last twodecades and the data rates as well as the quality of service (QoS) requirements are continuouslygrowing. Multiple-input multiple-output (MIMO) techniques in combination with orthogonalfrequency-division multiplexing (MIMO–OFDM) have been identified as a promising approachfor high spectral efficiency wideband systems.
The optimal detection method for a coded MIMO–OFDM system with spatial multiplexing(SM) is the maximum a posteriori (MAP) detector, which is often too complex for systems withhigh order modulation. Suboptimal linear detectors, such as the linear minimum mean square error(LMMSE) criterion based detection, offer low complexity solutions, but have poor performancein correlated fading channels. A list sphere detector (LSD) is a tree search based soft outputdetector that can be used to approximate the MAP detector with a lower computationalcomplexity. The benefits of the more advanced detectors can be realized especially in a low SNRenvironment by, e.g., increasing the cell coverage. In this thesis, we consider the linear minimummean square error (LMMSE) criterion based detectors and more advanced LSDs for detection ofSM transmission.
The LSD algorithms are not as such feasible for hardware implementation. Therefore, weidentify the design choices that relate to the performance and implementation complexity of theLSD algorithms. We give guidelines to the LSD algorithm design and propose the proper trade-off solutions for practical wireless systems. The more stringent requirements call for furtherresearch on architectures and implementation. In particular, it is important to address theparallelism and pipelining factors in the architecture design to enable an optimal trade-off betweenused resources and operating speed. We design pipelined systolic array architecture for LMMSEdetector algorithms and efficient architectures with given algorithm properties for the LSDalgorithms.
We consider the VLSI implementation of the algorithms to study the true performance andcomplexity. The designed architectures are implemented on a field programmable gate array(FPGA) chip and CMOS application specific integrated circuit (ASIC) technology. Finally, wepresent some measurement results with a hardware testbed to verify the performance of theconsidered algorithms.