Hae:

Oulun yliopiston väitöskirjat

ON-CHIP TESTING OF A/D AND D/A CONVERTERS, ACTA UNIVERSITATIS OULUENSIS C Technica 365

ISBN-13:	978-951-42-6305-7
Kieli:	englanti
Kustantaja:	Oulun yliopisto
Oppiaine:	Tekniikka, matematiikka
Painosvuosi:	2010
Sidosasu:	pehmeäkantinen
Sijainti:	Print Tietotalo
Sivumäärä:	194
Tekijät:	KORHONEN ESA

24.00 €

The static linearity testing of analog-to-digital and digital-to-analog converters (ADCs and DACs)has traditionally required test instruments with higher linearity and resolution than that of thedevice under test. In this thesis ways to test converters without expensive precision instrumentsare studied. A novel calculation algorithm for the ADC differential non-linearity (DNL) andintegral non-linearity (INL) estimation is proposed. The algorithm assumes that two stimuli withconstant offset between them are applied to the ADC under test and that the code densityhistograms for both stimuli are recorded. The probability density function (PDF) of the stimulusis then solved using simple calculations so that DNL and INL of the ADC can be estimated withouta priori known stimuli. If a DAC is used to generate the stimulus to ADC, all inputs and outputsare digital and the new algorithm can be used to obtain the PDF of the DAC output. Moreover, thePDF of DAC actually characterizes its INL and DNL so that this all-digital test configurationenables a simultaneous testing of both converters thanks to the new algorithm. The proposed algorithm is analyzed thoroughly both mathematically and by carrying outseveral simulations and experimental tests. On the basis of the analysis it is possible toapproximate the impending estimation error and select the optimal value for the offset between thestimuli. In theory, the accuracy of the algorithm proposed equals that of the standard histogrammethod with ideal stimulus, but in practice, the accuracy is limited by that of the offset betweenthe stimuli. Therefore, special attention is paid to development of an accurate and small offsetgenerator which enables ratiometric test setup and solves the problems in the case of referencevoltage drift. The proposed on-chip offset generator is built using only four resistors and switches.It occupies 122·22 ìm2 in a 130 nm CMOS process and accuracy is appropriate for the INL testingof 12-bit converters from rail-to-rail. Based on the analysis of the influence of resistor non-linearity on the accuracy of offset, it is possible to improve the offset generator further. Withdiscrete resistors, the INL of 16-bit ADCs was tested using a 12-bit signal generator. The proposed simple algorithm and tiny offset generator are considered to be important stepstowards built-in DNL and INL testing of ADCs and DACs.

Takaisin